As memory devices become more dense it is necessary to decrease the size of circuit components. One way to retain the storage capacity of a dynamic random access memory (DRAM) device and decrease its size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. In order to achieve the charge storage efficiency needed in 256 megabit(Mb) memories and above, materials having a high dielectric constant, typically greater than 50, can be used as the dielectric layer to insulate the storage node electrode and cell plate electrode of the storage cell capacitor one from the other. A dielectric constant is a value characteristic of a material and is proportional to the amount of charge that can be stored in the material when it is interposed between two electrodes. Ba.sub.x Sr.sub.(1-x) TiO.sub.3 [BST], BaTiO.sub.3, SrTiO.sub.3, PbTiO.sub.3, Pb(Zr,Ti)O.sub.3 [PZT], (Pb,La) (Zr,Ti)O.sub.3 [PLZT], (Pb,La) TiO.sub.3 [PLT], KNO.sub.3, and LiNbO.sub.3 are among some of the high dielectric constant materials that can be used in this application. These materials have dielectric constant values above 50 and will likely replace the standard Si.sub.3 N.sub.4, SiO.sub.2 /Si.sub.3 N.sub.4, Si.sub.3 N.sub.4 /SiO.sub.2, or SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 composite films used in 256 kilobits (Kb) to 64 megabits (Mb) generations of DRAMs. Si.sub.3 N.sub.4 and SiO.sub.2 /Si.sub.3 N.sub.4 composite films have dielectric constant values of 7 or less. The storage node and cell plate electrodes are also referred to as first and second electrodes.
Unfortunately BST is incompatible with existing processes and can not be simply deposited on a polysilicon electrode as was the case for the lower dielectric constant materials, such as Si.sub.3 N.sub.4 and SiO.sub.2 /Si.sub.3 N.sub.4 composite layers. In the storage cell capacitor incorporating BST, described in the IDEM-91 article entitled, A STACKED CAPACITOR WITH (Ba.sub.x Sr.sub.1-x) TiO.sub.3 FOR 256M DRAM by Koyama et al., the storage node electrode typically comprises a layer of platinum overlying a tantalum layer which, in turn, overlies a polysilicon plug. Platinum is used as the upper portion of the first electrode since it will not oxidize during a BST deposition or subsequent anneal. An electrode that oxidizes would have a low dielectric constant film below the BST, thereby negating the advantages provided by the high dielectric constant material. The tantalum layer is introduced to avoid Si and Pt inter-diffusion and to prevent the formation of SiO.sub.2 on top of the platinum surface. In addition,, the platinum protects the top surface of the tantalum from strong oxidizing conditions during the BST deposition. FIG. 1 depicts the stacked storage node electrode comprising tantalum 1, platinum 2 (Ta/Pt) overlying the polysilicon plug 3.
However, the sidewalls 4 of the tantalum 1 formed during this process are subject to oxidation during the subsequent deposition of the BST layer. Since the tantalum 1 oxidizes the polysilicon plug 3 is also susceptible to oxidation. When portions of the polysilicon plug 3 and tantalum 1 are consumed by oxidation the capacitance of the storage cell capacitor is decreased since the storage node electrode is partially covered by a low dielectric constant film. Therefore the memory device cannot be made as dense. In addition, the storage node contact resistance increases drastically.